Below, a 2.5D solution: 3D memory chip attached to interposer (photo courtesy of Tezzaron)
About the 3D-IC Alliance
The 3D-IC Alliance is a consortium of integrated circuit designers, developers, and manufacturers. Its objective is to promote standards for three-dimensional integrated circuits (3D-ICs) in order to accelerate their availability and acceptance. Industry-wide standards would allow virtually any semiconductor vendor to implement 3D technology.
Non-members are invited to join the 3D-IC Alliance. Membership is free! We ask only that you be willing to read and comment on new standards as they appear.
The first standard released by the Alliance is IMIS™ (Intimate Memory Interconnect Standard), available for immediate download on the Standards page. This standard reflects our initial focus on the standardization of vertical interconnect requirements such as pad sizing and spacing, interconnect keepouts, and materials. The Alliance intends to define a family of interconnect standards to accommodate embedded interconnect systems and various methods for adding backside or frontside interconnect. In January of 2010, a press release from SEMI praised IMIS™: "This standard lays the cornerstone for memory-to-logic 3D integration and establishes a basis for future collaborative efforts in the industry."
The 3D-IC Alliance plans to publish additional specifications for ICs and/or wafers that are designed to be stacked and vertically integrated. Any ICs or wafers that are processed and designed to these standards should be 3D integratable by most (if not all) Alliance members. The Alliance may also work to produce specific protocols and signaling and electrical specifications, allowing broad adoption and interchange between various die-level or wafer-level vendors.
Membership applications are welcome!
For other inquiries, send e-mail to: info@3D-IC.org
3D-IC Alliance Founding Members:
© 2005-2014 3D-IC Alliance. All rights reserved. Revised: January 25, 2016