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Papers & Articles about 3D ICs

(Listed in reverse chronological order)

New listings highlighted like this

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TSV forecast for millions of wafers
Solid State Technology blog, February 22, 2008

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3D IC & Packaging Newsletter
Bi-monthly publication by Micronews

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3D-ICs and Integrated Circuit Security (.pdf format)
Tezzaron white paper, February 7, 2008

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Roadmap Dictated by Flash, More Than Moore
Semiconductor International, January 25, 2008

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3D interconnect session brings new topic to IITC
EDN, January 25, 2008

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3D Packaging - Which Way to Go?
Advanced Packaging, January 21, 2008

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IC Packaging Gets Ready For The Big Squeeze
electronic design, January 17, 2008

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Interconnect Conference Expands Scope
Semiconductor International, January 2, 2008

 2007

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Market Trends & Cost Analysis for 3DIC & TSV Integration (slide presentation, pdf format)
EPTC 2007 Packaging conference, December, 2007

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More TSV commercial capacity on line.....     and
3D discussions in the valley... continued
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A Rose by any other name is not 3D IC Integration
Semiconductor International blog, November/December, 2007

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3D IC Packaging - Unavoidable Technology For Miniaturization and Increased Performance
Electronics.ca Publications press release, November 27, 2007

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SiP, 3-D IC stacking combat ever-shrinking form factors
EE Times, November 26, 2007

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3D integration will affect IC, MEMS, and image sensors markets
Yole Developpement, November 21, 2007

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50$ 3D bond coming ??; Intel announces "...we are ready"
Semiconductor International blog, October 29, 2007

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EDA's big three unready for 3D chip packaging
EE Times Asia, October 25, 2007

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Moore's Law to head z-ward?
Solid State Technology, October 2007 

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3-D Goes Beyond Simplifying Interconnect
Semiconductor International, October 18, 2007

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IMEC Explores the 3D integrated circuit, one challenge at a time
EDN blog, October 18, 2007

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IC Packages Feel the Squeeze
Electronic Design, October 11, 2007

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Some things Need Repeating...
Semiconductor International blog, September 29, 2007

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A New Era: 3D TSV Interconnects (slide presentation, pdf format)
SEMATECH Symposium Japan, September 13 2007

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3D: A Whole World of Challenge
Semiconductor International blog, September 6, 2007

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3-D Integration: What Direction Will It Take? (webcast)
Semiconductor International, September 5, 2007

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A New Era: 3D TSV Interconnects   (slide presentation, pdf format)
SEMATECH Symposium Japan, September 2007

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The Greatness of Verticalness
Semiconductor International, August 2007

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3D IC Report  (Sample only, .pdf format)
Yole Développement, 2007

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Enabling 3-D Design
Semiconductor International, August 2007

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Several good white papers on 3D published in Volume 23 of
Future Fab International, July 2007

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CEA-Leti 3D Activites and Roadmap (slide presentation, pdf format)
EMC-3D Technical Symposium, June 2007

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3-D Chip Stacking with Wafer-to-Wafer Integration
Semiconductor International, June 2007

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Design in the age of 3-D Stacking
EE Times, June 2007

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Market trends for 3D stacking  (slide presentation, pdf format)
EMC 3D, June 2007

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3-D Through-Silicon Vias Become a Reality
Semiconductor International, June 2007

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Posturing & Positioning in 3-D ICs
Semiconductor International, April 2007

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Vertical Stacking to Redefine Chip Design
Nikkei Electronics Asia, April 2007

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SEMATECH Offers Program-Based Memberships in 3D Interconnect Program
SOCcentral, March 2007

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What is 3D IC integration and what metrology is needed?
CEA presentation, March 2007

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3D could stack deck for IC makers in fight to tame interconnect
EE Times, February 2007

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EMC-3D Consortium Targets Cost-Effective TSV Interconnects
Semiconductor International, February 2007

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Evolving Roles of IC Packaging in 3D Interconnection Systems  (slide presentation, pdf format)
Pan Pacific Microelectronics Symposium, January 2007

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Making the Business Case for 3D
Future Fab International, January 2007

 2006

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3-D Integration Could Improve Yields
Semiconductor International, December 2006

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Three-Dimensional Integrated Circuits
IBM Journal of Research and Development, July/September 2006

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Wafer-Level 3-D Integration Moving Forward
Semiconductor International, October 2006

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Designing in the Third Dimension
EDN Asia, October 2006

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3D Interconnection and Packaging
IMEC presentation, September 2006

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Deep Silicon Etching Gets Ready for 3-D ICs
Semiconductor International, September 2006

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3-D Requires System Rethink
EE Times, August 2006

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Focus on: 3D Integration (a collection of articles)
Semiconductor International, August 2006

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Fermilab Initiatives in 3D Integrated Circuits
ILC Vertex Workshop, May 2006

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Mapping Progress in 3D IC Integration
Solid State Technology, April 2006

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Wafer Bonding Reaches New Highs... and Lows
Chip Scale Review, April 2006

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Design Space Exploration for 3D Architectures
ACM Journal on Emerging Technologies, April 2006

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Sematech Unveils 3D Initiative
Electronic News, February 2006

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The Impact of 3-Dimensional Integration on the Design of Arithmetic Units
Georgia Institute of Technology, January 2006

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Sematech targets infrastructure for 3-D chips
EE Times, January 2006

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Focus on: 3-D Integration (a collection of articles)
Semiconductor International, January 2006

For earlier listings (2003-2005), click here

© 2005-2008 3D-IC Alliance. All rights reserved.  Revised: February 22, 2008

 

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